The present invention relates to a method of testing memory cells with a hysteresis curve, in which test voltages are applied to the memory cell during a testing procedure.
Such memory cells with a hysteresis curve may be ferroelectric memory cells, magnetic memory cells, etc. The invention can generally be readily used for all memory cells of which the storage medium has hysteresis properties.
A ferroelectric memory cell contains a ferroelectric storage capacitor and a selection transistor, which is connected to a bit line and at a gate of which a word line is connected. The electrode of the storage capacitor that is not connected to the selection transistor is referred to as plate and is at a pulsed potential. If appropriate, the plate may also have a fixed voltage applied to it.
An information bit xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is stored in the ferroelectric storage capacitor according to the state of polarization of the latter.
The memory cell is activated for example by applying a positive voltage pulse to the plate and raising the word line to a high voltage level. The selection transistor opens and the storage capacitor discharges its charge to the bit line. Depending on the information stored in the storage capacitor, the charge discharged to the bit line may have a greater or smaller value, so that a voltage level V1 or V0 occurs on the bit line.
For optimum sensing of this voltage level on the bit line BL, which represents a data signal signifying a logical xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, the voltage level is compared with a reference signal, which usually has the value (V1+V0)/2. The reference signal may be generated, for example, independently for each pair of bit lines by two memory cells which are respectively storing signals corresponding to a logical xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. This information bit of a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is delivered to a pair of reference bit lines, which are shorted and consequently supply the voltage (V1+V0)/2 to both bit lines. The reference voltage (V1+V0)/2 is obtained from the reference memory cells before an actual reading operation on a word line for a memory cell begins.
The storage of a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d in the storage medium of the ferroelectric storage capacitor is based on the bistable behavior of the storage medium. For this purpose, the hysteresis curve of the ferroelectric storage capacitor, the polarization (in As) of the storage medium can be plotted as a function of the electric field strength (in V/m). By applying a suitable electric field (E) to the ferroelectric storage capacitor, two stable states xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d can be obtained after switching off the electric field E.
However, it must be noted at the same time that the hysteresis curve is not constant, but is subjected to an aging process (xe2x80x9cagingxe2x80x9d). The aging process depends on numerous factors, such as for example the number of reading/writing cycles executed with the ferroelectric storage capacitor, thermal and mechanical loads etc. The aging process has the effect that the hysteresis curve shrinks in its shape, which is referred to as relaxation, is shifted in the horizontal and/or vertical direction or is deformed horizontally/vertically. The last-mentioned aging effect is also referred to as xe2x80x9cfatiguexe2x80x9d.
The position of the stable states xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d is thus influenced by xe2x80x9cfatiguexe2x80x9d, i.e. the energy or charge recovered by reading the memory cell depends on xe2x80x9cfatiguexe2x80x9d.
Consequently, two minimum levels for the polarization, which have to exist in any event in order for correct reading of the logical information xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d to be possible from the storage capacitor. If the hysteresis curve is deformed horizontally/vertically due to xe2x80x9cagingxe2x80x9d as a result of xe2x80x9cfatiguexe2x80x9d in such a way that it lies below the minimum levels, such memory cells can no longer be correctly evaluated.
It is consequently important to segregate weak or substandard memory cells which can no longer be evaluated from the remaining memory cells and replace them by memory cells which are operating normally, that is for which the hysteresis curve extends over the minimum levels. Such segregation also increases the production yield, since, before they are dispatched for delivery, memory cells are subjected to a xe2x80x9cburn-inxe2x80x9d test in order that weak memory cells due to exposure to high external temperatures, voltages etc. are in any event aged rapidly, whereby these weak memory cells, that is in particular those memory cells which exhibit excessive xe2x80x9cagingxe2x80x9d, are identified. A repair of such weak memory cells is no longer possible at this late state of production, so that memories with weak memory cells must be discarded.
It is consequently of decisive importance to distinguish weak memory cells from normal memory cells as early as possible to allow them to be replaced by normal memory cells.
It is consequently the object of the present invention to specify a method of testing memory cells with a hysteresis curve which allows the most reliable possible detection of weak memory cells, that is in particular those memory cells which exhibit greater xe2x80x9cagingxe2x80x9d than usual, at an early time.
It is accordingly an object of the invention to provide a method of testing memory cells with a hysteresis curve that overcomes the disadvantages of the prior art methods of this general type, in which test voltages are changed in steps during the testing procedure in order to sense memory cells with a deformed hysteresis curve.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of testing a memory. The method includes the steps of applying a test voltage to a memory cell during a testing procedure; changing the test voltage in steps during the testing procedure and determining if the memory cell has a deformed hysteresis curve.
In the case of the method according to the invention, consequently, as soon as the cell array of the ferroelectric memory is realized in a chip, the memory is subjected to a testing procedure, in which the test voltage applied to the individual memory cells is changed in steps. Consequently, weak memory cells can be determined and, if need be, can still be replaced by normal memory cells. A particularly significant aspect of the invention is the step-by-step or incremental (or decremental) changing of the internal voltage present at the memory cells in the chip, whereby weak cells can be established without using excessive testing time.
The test voltages may be applied in various ways: for example, it is possible to change the plate voltage present at the storage capacitor in steps. Similarly, a reference voltage, with which a reading voltage read out from the memory cell is compared, can be changed in steps. The voltage applied to a word line may also be changed in steps. Finally, it is also possible for a writing voltage applied to the memory cell to be changed in steps.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method of testing memory cells with a hysteresis curve, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing.